library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity incrementer is
    Port ( X : in  STD_LOGIC_VECTOR(7 downto 0); --вход
           F : out  STD_LOGIC_VECTOR(7 downto 0)); --выход
end incrementer;

architecture BEH of incrementer is
begin
    F <= STD_LOGIC_VECTOR(unsigned(X) + 1);
end BEH;